SFMSHD=0, SFMSLD=0, SFMSW=0000
Chip Selection Control Register
| SFMSW | Selection of a minimum high-level width of the QSSL signal 0 (0000): 1 x QSPCLK 1 (0001): 2 x QSPCLK 2 (0010): 3 x QSPCLK 3 (0011): 4 x QSPCLK 4 (0100): 5 x QSPCLK 5 (0101): 6 x QSPCLK 6 (0110): 7 x QSPCLK 7 (0111): 8 x QSPCLK 8 (1000): 9 x QSPCLK 9 (1001): 10 x QSPCLK 10 (1010): 11 x QSPCLK 11 (1011): 12 x QSPCLK 12 (1100): 13 x QSPCLK 13 (1101): 14 x QSPCLK 14 (1110): 15 x QSPCLK 15 (1111): 16 x QSPCLK |
| SFMSHD | QSSL signal release timing selection 0 (0): Releases QSSL 0.5*SCK after the last rising edge of QSPCLK 1 (1): Releases QSSL 1.5*SCK after the last rising edge of QSPCLK |
| SFMSLD | QSSL signal output timing selection 0 (0): Outputs QSSL 0.5*SCK before the first rising edge of QSPCLK 1 (1): Outputs QSSL 1.5*SCK before the first rising edge of QSPCLK |